1. Field of the Invention
The present invention relates to a semiconductor memory device and manufacturing method, and more particularly, to a semiconductor memory device and method for manufacturing a semiconductor memory device that is resistant to oxidation of the bit lines.
2. Description of the Related Art
In manufacturing a dynamic random access memory (DRAM), in order to increase the operational speed of a device, a bit line is generally formed by a polycide structure obtained by depositing an impurity-doped polysilicon and a low-resistance silicide.
FIG. 1 is a sectional view for explaining a method for manufacturing a conventional DRAM.
Referring to FIG. 1, a transistor (not shown) is formed by a conventional manner on a semiconductor substrate 100 divided into an active regions (not shown) and field regions (not shown) by field oxide layers 12. Next, polysilicon is deposited on the resultant structure and then patterned, thereby forming a pad 14 for connecting a storage electrode to the active region (source region) of the semiconductor substrate 100. After the pad is formed, an insulating material is deposited on the resultant structure and then planarized, thereby forming a first insulating layer 16 for insulating the transistor from another conductive layer. To facilitate the planarization, the first insulating layer 16 may be formed of a fluid insulating layer, e.g., borophosphosilicate glass (BPSG) or undoped silicate glass (USG).
Next, a bit line contact (not shown) and bit line 18 and 20 is formed by a conventional method and then a planarized second insulating layer 22 is formed on the resultant structure. The bit line is formed by depositing a doped polysilicon layer 18 and a silicide layer 20 on the first insulating layer 16, and the second insulating layer 22 is formed in a similar manner to the first insulating layer 16. Subsequently, a nitride layer 24 and an oxide layer 26 are sequentially deposited on the resultant structure.
Next, the oxide layer 26, the nitride layer 24, the second insulating layer 22 and the first insulating layer 16 are anisotropically etched by photolithography to form a contact hole exposing the pad 14. A nitride layer is deposited on the surface of the resultant structure having the contact hole to form a spacer 28 on the sidewall of the contact hole. The spacer 28 helps prevent the oxidation of the bit lines by oxygen diffused through the sidewall of the contact hole.
Next, a polysilicon layer is deposited on the resultant structure, and patterned by photolithography to form a storage electrode 30. A dielectric layer 32 and a plate electrode 34 are formed on the storage electrode 30 by a conventional method. The dielectric layer 32 may be formed in an NO structure obtained by depositing a nitride layer and by forming a thermal oxide layer, for the purpose of improving capacitor characteristics. The nitride layer is typically formed by a chemical vapor deposition (CVD) method, and the oxide layer is formed by a thermal oxidation method. Other types of dielectrics such as ONO may also be used.
As semiconductor memory devices become highly integrated, misalignment may occur during the photolithography for forming the storage electrode 30. FIG. 2 is a sectional view showing an example of such misalignment. In FIG. 2, if misalignment occurs between the etching mask for storage electrode 30 and the contact hole, an overetch may occur on the nitride layer spacer 28 when the storage electrode 30 is patterned by etching. Accordingly, the second insulating layer 22 is exposed at the sidewall of the contact hole. If the second insulating layer 22 is exposed, the nitride layer is deposited more thinly on the exposed second insulating layer 22 than on other layers when the dielectric layer 32 is formed in a subsequent step. This phenomenon is caused by the different deposition rates of the nitride layer, depending on the composition of the underlayer.
FIG. 3 shows the deposition characteristics of the nitride layer for both a wafer underlayer and a BPSG underlayer. In FIG. 3, “A” indicates the thickness of the nitride layer deposited on a bare wafer, and “B” indicates the thickness of the nitride layer deposited on a BPSG layer. As shown in the graph for a deposition time of 50 minutes, when the nitride layer is deposited on the bare wafer to a thickness of about 50 angstroms, the nitride layer is deposited to be only 37 angstroms thick on the BPSG layer. Therefore, as shown in FIG. 2, the second insulating layer 22 is susceptible to oxygen diffusion because the oxygen used during thermal oxidation in forming the oxide in the dielectric layer 34 may penetrate into a portion of second insulating layer 22 where the nitride layer is deposited thinly. The bit line 18 and 20 may become oxidized, thereby changing its electrical characteristics. The resulting increased resistance in the bit line may cause the memory device to become inoperative or unreliable.